1. Field of the Invention
The present invention relates to testing of integrated circuit devices. More specifically, but without limitation thereto, the present invention relates to a method of isolating sources of variance in parametric test data measured from a semiconductor wafer used in the manufacture of integrated circuits.
2. Description of Related Art
Semiconductor devices are typically manufactured in several processing steps. Each of these processing steps contributes variability to the performance and robustness of the resulting products. Microelectronic parametric test (E-test) structures are frequently incorporated into production wafers to monitor specific physical phenomena during the processing steps. Although the E-test structures are designed to isolate specific physical phenomena, in practice there is usually a high degree of correlation among test parameters due to the influence of multiple variance mechanisms commonly found in any E-test structure. The high degree of correlation among test parameters limits the capability to diagnose production process variation using conventional E-test and lot-equipment-history (LEH) data. As a result, traditional statistical analysis methods, such as principal component analysis (PCA), are unable to isolate sources of variance in the test data to identify the underlying physical mechanisms, for example, in the processing steps used to manufacture integrated circuits.